Teaching Experience

Academic Achievements

• Rumi Rastogi, Sujata Pandey, Mridula Gupta, “Design Techniques for Power-Gated Nanoscale Low Power Circuits” Micro and Nanosystems, Vol. 11, No. 2, 2019, pages: 1-10 (Scopus Indexed)
• Rumi Rastogi, Sujata Pandey, Mridula Gupta, “Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits”, Accepted in Nanoscience and Nanotechnology-Asia, vol. 9, pages 1 – 13, 2019 (Scopus Indexed)
• Rumi Rastogi, Sujata Pandey “Novel Design Techniques for Noise-Tolerant Power-Gated CMOS Circuits” Journal of Semiconductors, Vol. 38, No. 1, Jan-2017 pages:(015001)1-7.(Scopus Indexed)
• Rumi Rastogi and Sujata Pandey, “A Novel Multi-Threshold CMOS Based 64-Bit Adder Design in 45nm CMOS Technology for Low Power Application”, International Journal of Simulation Systems, Science & Technology, Vol. 17, No. 33, pages: 14.1-14, 2017 (Scopus Indexed)
• Satender Vats and Rumi Rastogi, “Ground bounce noise minimization in low power MTCMOS circuits in 45nm technology,” International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 5, Issue 4, April 2016.

• Rumi Rastogi, Sujata Pandey and Mridula Gupta “A New Charge-Recycling Approach for Reactivation-Noise Reduction”, IEEE Third International Conference on Contemporary Computing and Informatics, IC3I- Oct. 2018, Amity University Gurgaon.
• Rumi Rastogi and Dr. Sujata Pandey “Implementing Low Power Dynamic Adders in MTCMOS Technology”, IEEE International Conference on Electronics and Communication Systems, ICECS-2015, Coimbatore, India.
• Rumi Rastogi and Dr. Sujata Pandey “Leakage power reduction in MTCMOS based high speed adders”, IEEE International Conference on Computer, Communication and Control, IC-4-2015, Indore, India.
• Rumi Rastogi, “A new linear CMOS transconductor”, International Conference on Wireless networks and Embedded systems WECON 2009, 23rd and 24th oct, 2009, Chandigarh, India.

Areas of Interest: